Marley Lobão de Sousa
@MarleyLobaoBSc. in Electrical Engineering from UFCG. Interested in digital microelectronics.
Language Breakdown
Lines of code distribution across 7 owned repositories
T-Shaped Developer
T-shapedDeep in SystemVerilog with broad versatility
Collaboration Network
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Repos
14
PRs
0
Growth
+18%
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Coding Streak
Contribution activity over the past year
Jonathas Silveira
@JEvSilv
Nelson Campos
@nelsoncsc
Maísa Lobão
@maisalobao
briba
@lyangmdrs
Edson Porto da Silva
@edsonportosilva
Top Repositories
This repository is meant for learning UVM using SystemVerilog. Through a verification environment, some hardware verification concepts are applied for a calculator with the four basic operations.
This repository organizes the ChipVerify website code so that it is executable in a verification environment that uses the Register Abstraction Layer (RAL) in frontdoor and backdoor modes, as well as other features.
Through a verification environment, this repository uses UVM to handle with multiple clock domains and virtual sequences.
These repository contains some experiments related to the code from digital coherent optical systems book.
Material de apoio e códigos de simulação utilizados nas aulas da disciplina Transmissão Digital da Informação (TDI) do curso de Engenharia Elétrica da Universidade Federal de Campina Grande (UFCG).
Tranining Completion Project : : Verification of AXI Direct Memory Access (DMA) using UVM
This is a project for the Data Acquisition and Interface Systems subject. Monitor the temperature and the cleanining and feeding time of your aquarium.
This repository organizes the ChipVerify website code so that it is executable in a verification environment that uses only the Systemverilog language resources to verify some design as an example.
This code uses a SystemC and RTL block in the same top simulation file.
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